As semiconductor device manufacturing technology continues to evolve toward the direction of enabling further shrinkage of footprint and/or size of devices that it manufactures, semiconductor devices such as, for example, transistors are becoming smaller than ever before in overall structural size. Consequently, in the meantime, structure related parasitic characteristics of these smaller devices are becoming increasingly important in influencing and sometimes determining application of these devices. For example, capacitance that may be found in the form of gate-to-source or gate-to-drain has come to play an ever bigger role of impacting operational speed of a transistor, energy consumption of any integrated circuit (IC) that makes use of that transistor, and other aspects of performance. In general, gate-to-source or gate-to-drain capacitance is affected, and determined, by the size of gate and source/drain contact as well as characteristic of the dielectric material, represented typically by its dielectric constant, between the gate and the source/drain contact. For example, in a conventional field-effect-transistor (FET), the dielectric material may include, among others, spacers at the sidewalls of the gate.